This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Generally, in an attempt to inhibit degradation of read and write margins, some memory devices have attempted to support read and write operations by delaying data access signals in the signal path to recover read margins. This delay typically results in a timing penalty for data access. Similarly, in an attempt to recover write margins, some memory devices have attempted to increase an amount of write assist, which typically leads to increased area penalty, power penalty and implementation complexities. Thus, there exists a need to improve integrated circuitry to enable recovery of degraded read and write margins in a more efficient manner.